It is a known use of Phase Lock Loops (PLL) as a programmable clock generator to generate a variety of clocks and responses from a printer engine emulator card back to cards that normally would drive a print engine. FIG. 1 illustrates a conventional PLL based clock generator. A reference oscillator 102 generates a reference frequency to a PLL 101. Typically, the reference oscillator 102 is fixed for a wide range of target clock signals. For each printer speed and resolution, there is a corresponding clock frequency to be generated by the PLL 101. To generate this clock frequency, the reference frequency, a set of multipliers 103, and an output divider 104 are selected and applied. The multipliers 104 are usually in the form of N/M or some variation, and each has a specified range. For example, both M and N can each have a value in the range of 1 to 256, and the output divider “O” can have the value 2, 3, 4, 5, 6, 7, 8, or 10. For optimum flexibility in adjusting the clock frequency, values of M, N and O near the middle of their respective ranges are desired. However, for PLL's with limited range, the middles of the ranges are narrow for a given reference frequency and target clock frequency. This can result in the loss of accuracy in the clock frequency, especially for high printer speeds or resolutions.
Accordingly, there exists a need for a method and system for clock scaling to optimize PLL clock generation accuracy. The method and system should provide a greater granularity of control of and result in a smaller error in the output frequency of the PLL. The present invention addresses such a need.